This invention relates multi-stage linear amplifiers subject to widely varying load conditions and particularly to stabilized linear voltage regulator circuits, and more particularly low drop-out (LDO) linear voltage regulator circuits incorporating stabilization.
Shown in FIG. 1 is a conventional circuit topology of an LDO. A PMOS pass device MP receives unregulated input voltage VIN at the source terminal S. The load of the LDO regulator, represented by resistance RL, is tied to the drain terminal D of M. Regulated output voltage VOUT generated at the drain of MP is divided between resistors RI and R2, and the resulting feedback voltage VFB is compared with a reference voltage VREF at the inputs of a high-gain error amplifier AE of voltage gain A. The output voltage VA of AE drives the gate of Mp to close the negative feedback loop needed for regulating the output voltage. Capacitor CL shown in parallel with the load serves the purpose of improving the transient response of the LDO regulator.
Unless supplemented with a proper frequency compensation scheme, the regulation loop of an LDO regulator cannot be stable with an adequate phase margin because the loop-gain transfer function (LGTF) contains at least two poles at frequencies lesser that its unity-gain frequency. The fact that the frequency of the load pole associated with the output of LDO regulator increases with load current IL further accentuates this problem.                A common frequency compensation technique applied to LDO regulator stabilization is to introduce a transfer function zero to the LGTF by utilizing a load capacitance CL with a parasitic equivalent series resistance (ESR). However, the ESR values needed for this purpose are available only in relatively expensive and bulky electrolytic or tantalum capacitors. Ceramic capacitors that are favored due to their low cost and small form factor are unsuitable for this purpose because their ESR is much lower than needed for stabilizing an LDO regulator. For this reason, an LDO regulator must be internally compensated if a ceramic load capacitor is to be deployed.        
A common internal compensation technique used in prior art (U.S. Pat. No. 6,300,749B1, U.S. Pat. No. 6,556,083 B2, U.S. Pat. No. 6,603,292 B1, and U.S. Pat. No. 6,707,340 B1) is to modify the LGTF with a fixed-frequency pole and a zero whose frequency increases with load current IL. The adaptive zero compensates for the adverse effect of the variable load pole by tracking it. This technique is illustrated in FIG. 2. The error amplifier has a first gain stage AE1 and a second buffer stage AE2. A compensation network is connected between the output of the first stage and signal ground. This network is a series combination of a compensation capacitor CC of fixed capacitance, and a voltage-controlled resistor RC of variable resistance. Since CC blocks the dc path of RC, RC operates without any dc current. However, the conductance of RC is adjusted to be an increasing function of IL by a current-sensing bias circuit S. In this manner the frequency of the zero created by CC and RC is made an increasing function of IL.
The patents cited herein differ mainly in techniques for sensing the load current and for controlling the RC with the sensed current. However, they are all similar in deploying a buffering second stage. The very low output resistance of this stage helps move the pole at the input of MP to a frequency much higher than the unity-gain frequency of the LGTF despite the presence of a very large capacitance at this node. This pole thus ceases to be influential on stability. Since, however, low output resistance precludes high gain, a buffer stage can provide only a very limited gain close to unity. As an undesirable consequence of a buffering second stage, therefore, the error amplifier is left with a single gain the first stage to provide all or most of its overall loop gain. The overall loop gain is thus severely limited. A second undesirable property of a buffering second stage is that no simple buffer topology can match a simple gain stage in the extent of output range. A rail-to-rail output range is indeed needed for minimizing the footprint of the pass transistor while maintaining a wide load range with a small dropout voltage.
It is therefore highly desirable in LDO design to utilize an error amplifier with two high gain stages, none of which being a buffer, and still maintain stability with a reasonable phase margin over a wide load range.